Datacom Systems D56 Specifications

Rev. 1.3 6/12 Copyright © 2012 by Silicon Laboratories Si5040Si504010 Gbps XFP TRANSCEIVER WITH JITTER ATTENUATORFeaturesComplete, high-performance, l

Si504010 Rev. 1.3Figure 3. Receiver Differential Output Mask (RD)Normalized Time (UI)Absolute Amplitude0.0 X1 X2 1–X2 1.01–X1Y2Y10–Y1–Y2

Si5040100 Rev. 1.314. Pin Descriptions: Si5040Figure 24. Si5040 Pin Configuration (Transparent Top View)Table 13. Si5040 Pin DescriptionsPin Name Typ

Si5040Rev. 1.3 1012 RX_LOL DO LVTTL Receiver Loss of Lock (Active High).This output is asserted when the receiver path is in the loss-of-lock state. I

Si5040102 Rev. 1.3Power and Ground1, 5, 8, 17, 20, 23, 28, 31GND P GND Supply Ground.Connect to system GND. Ensure a very low impedance path for optim

Si5040Rev. 1.3 10315. Ordering GuidePart Number* Package Lead-Free TemperatureSi5040-D-GM 32-lead LGA Yes –40 to 95 °C*Note: Add an “R” at the end o

Si5040104 Rev. 1.316. Package Outline: Si5040Figure 25 illustrates the package details for the Si5040. Table 14 lists the values for the dimensions s

Si5040Rev. 1.3 10517. Recommended VDD Power Supply FilteringBecause of the internal bypass capacitance and voltage regulators, the external supply by

Si5040106 Rev. 1.3DOCUMENT CHANGE LISTRevision 0.5 to Revision 0.8 Updated final specification numbers for TBD items. Updated register name in Regis

Si5040Rev. 1.3 107Revision 0.86 to Revision 1.2 Removed sections 5.8.3 and 6.4.3 since fast acquisition is no longer supported. Clarified operation

Si5040108 Rev. 1.3CONTACT INFORMATIONSilicon Laboratories Inc.400 West Cesar ChavezAustin, TX 78701Tel: 1+(512) 416-8500Fax: 1+(512) 416-9669Toll Free

Si5040Rev. 1.3 11Table 5. AC Characteristics—TXDOUT (Transmitter Output)(VDD= 1.8 V +5/–10%, TA= –40 to 95 C)Parameter Symbol Test Condition Min Typ

Si504012 Rev. 1.3Table 6. AC Characteristics–TD (Transmitter Input)Parameter Symbol Test Condition Min Typ Max UnitTX Path Data Rate 9.80 9.95 11.35 G

Si5040Rev. 1.3 13Figure 4. XFI Sinusoidal Jitter Tolerance (UIPP)Figure 5. Transmitter Differential Input Mask (TD)Si5040 TD Jitter Tolerance (Typ)0.0

Si504014 Rev. 1.3 Table 8. AC Characteristics—I2C Bus Lines (SD, SCK)(VDD= 1.8 V +5/–10%, TA= –40 to 95 C)Parameter Symbol Test Condition Min Typ Max

Si5040Rev. 1.3 15Figure 6. Serial Microcontroller Interface Timing DiagramFigure 7. SPI-Like Interface Write/Set Address CommandFigure 8. SPI-Like Int

Si504016 Rev. 1.3Table 10. Thermal CharacteristicsParameter Symbol Test Condition Value UnitThermal Resistance Junction to Ambient JAStill Air 50 C/

Si5040Rev. 1.3 173. Typical Application SchematicSI5040RD-GND6RD+GND5TD-TD+GND4SCKSPSELNCNCVDD2REFCLK+REFCLK-VDD1INTRPTGND3RXDIN+RXDIN-GND2VDDIORX_LO

Si504018 Rev. 1.34. Functional DescriptionThe Si5040 XFP transceiver is a single-chip, bidirectional signal conditioner for use in XFP modules as def

Si5040Rev. 1.3 195. ReceiverThe Si5040 receiver includes a programmable equalizer, a high-sensitivity limiting amplifier, clock and datarecovery unit

Si50402 Rev. 1.3

Si504020 Rev. 1.35.2. Limiting AmplifierThe Si5040 incorporates a high-sensitivity differential limiting amplifier with sufficient gain to allow dire

Si5040Rev. 1.3 21Figure 11. Algorithm to Clear dLOSThe receiver may be programmed to perform any of the following consequent actions upon declaring RX

Si504022 Rev. 1.3Figure 12. CDR and VCO Behaviors Upon Declaring LOS (1 of 2)Figure 13. CDR and VCO Behaviors Upon Declaring LOS (2 of 2)LOS=1?YLOLonL

Si5040Rev. 1.3 23Figure 14. Receive and Transmit CDR and VCO Behaviors Upon Declaring LOL5.5. Receiver Slice ControlIn order to optimize the bit erro

Si504024 Rev. 1.35.6. Clock and Data Recovery (CDR)The Si5040 integrates a CDR to recover the clock and data from the input signal applied to RXDIN.

Si5040Rev. 1.3 255.8.1.1. Dynamic Register ControlThe dynamic control of RxLoopFAcq (Register 98) is required to ensure the locking performance of th

Si504026 Rev. 1.3Figure 15. RX LOS and LOL Block DiagramLOS (Bit 5, Register 9, Bit 0, Register 11 or Pin 3)Frequency Offset MonitorSqmLolReference Cl

Si5040Rev. 1.3 27Figure 16. TX LOS and LOL Block DiagramLOS (Bit 5, Register 137 orBit 0, Register 139)Frequency Offset MonitorTx Recovered ClockRefer

Si504028 Rev. 1.35.9. Receiver Phase AdjustThe Si5040 receiver supports programmable sample phase adjust. The sampling point may be advanced ordelaye

Si5040Rev. 1.3 296. TransmitterThe Si5040 transmitter includes an XFI-compliant, fixed-equalizer CDR for recovery of clock and data from the XFIchann

Si5040Rev. 1.3 3TABLE OF CONTENTSSection Page1. Si5040 Detailed Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Si504030 Rev. 1.36.4. Transmitter Loss of Lock (LOL)Transmitter LOL functions in different ways depending on whether the transmitter is operating in

Si5040Rev. 1.3 316.7. Timing Modes Of OperationFor maximum flexibility, the Si5040 supports three CMU timing modes that make it suitable for XFP modu

Si504032 Rev. 1.3Figure 18. Referenceless Mode (Mode 0)Figure 19. Synchronous Reference Clock (Mode 1)Figure 20. Mode 2CDREqualizerDSPLL® Jitter Atten

Si5040Rev. 1.3 337. Loopback ModesThe Si5040 supports XFI Loopback, Lineside Loopback, and Looptime modes.7.1. XFI LoopbackThe Si5040 is configured

Si504034 Rev. 1.39. Pattern Generation and CheckingThe Si5040 includes a programmable pattern generator and checker function in both the receiver and

Si5040Rev. 1.3 3510. Serial Microcontroller InterfaceDevice control and status monitoring is supported with a selectable I2C or SPI-like interface. S

Si504036 Rev. 1.310.2. SPI-Like InterfaceWhen configured in SPI-like control mode (pin SPSEL tied high), the control interface to the Si5040 is a 3-w

Si5040Rev. 1.3 3711. Interrupt FunctionalityAlarm Status bits (Register 9/137) are sampled by a 10 MHz clock to create the Interrupt Status bits (Reg

Si504038 Rev. 1.3Figure 23. Device Interrupt TreeRX_REFLOSInterrupt Status (sticky) bit(Register 5, bit 6) RX_REFLOS Interrupt mask bit(Register 4, bi

Si5040Rev. 1.3 3912. Programmable Power Down OptionsThe RX and TX paths can be powered down independently by programming RxPdn = 1 at Register 3, Bit

Si50404 Rev. 1.31. Si5040 Detailed Block DiagramRX CDRTX CDREqualizerRX Pattern Gen.RX Pattern CheckLADSPLLTM Jitter AttenuatorTX CMUXFI LB ClkXFI LB

Si504040 Rev. 1.313. Si5040 Register SummaryAny reserved bits listed in the table below or reserved registers (23, 54–55, 58–76, 78–83, 86–97, 99–105

Si5040Rev. 1.3 4130 RxtpChkConfig 2h Reserved Reserved Reserved Reserved Reserved tpSyncMask tpTimeBase[1:0]31 RxtpArbGenPtn AAh RxtpArbGenPtn[7:0]32

Si504042 Rev. 1.3132 TxintMask 0h Reserved refLOS LOS LOL fifoErr tpErrAlarm tpSyncLos sqmAlarm133 TxintStatus(Sticky Bits)0h Reserved refLOS LOS LOL

Si5040Rev. 1.3 43174 TxtpArbChkPtn AAh TxtpArbChkPtn[63:56]175 TxtpTargetErr FFh TxtpTargetErr[7:0]176 TxtpChkErrCnt N/A TxtpChkErrCnt[7:0]177 TxtpChk

Si504044 Rev. 1.3Reset settings = 0100 0000Reset settings = 0011 0000Register 0. Part IdentifierBitD7D6D5D4D3D2D1D0Name Identifier[7:0]Type RBit Name

Si5040Rev. 1.3 45Reset settings = 0101 1000Register 2. ChipConfig1Bit D7 D6 D5 D4 D3D2D1D0Name losOpenDrain intOpenDrain intEnable spiOpenDrain Reserv

Si504046 Rev. 1.3Reset settings = 0000 0000Register 3. RxChipConfig2BitD7D6D5D4D3D2D1D0Name RxPdnType RRRRRRRR/WBit Name Function7:1 Reserved Read ret

Si5040Rev. 1.3 47Reset settings = 0000 0000Register 4. RxintMaskBitD7D6D5D4D3D2D1D0NamerefLOS LOS LOL fifoErr tpErrAlarm tpSyncLos sqmAlarmTypeR R/W R

Si504048 Rev. 1.3Reset settings = 0000 0000Register 5. RxintStatus (Sticky Bits)BitD7D6D5D4D3D2D1D0Name refLOS LOS LOL fifoErr tpErrAlarm tpSyncLos sq

Si5040Rev. 1.3 49Reset settings = 0100 0000Register 6. RxCmuConfigBitD7D6D5D4D3D2D1D0Name cmuBandwidth[3:0] Reserved ReservedType R/W R R/WBit Name Fu

Si5040Rev. 1.3 52. Electrical SpecificationsFigure 1. Voltage MeasurementFigure 2. Rise/Fall Time MeasurementTable 1. Recommended Operating Condition

Si504050 Rev. 1.3Reset settings = 0001 0101Register 7. RxConfigBitD7D6D5 D4 D3 D2D1D0Name lolOnLOS ltrOnLOS CDRLTDATA uselolMode lolMode ltr rxRefclkE

Si5040Rev. 1.3 51Reset settings = 0000 0000Register 8. RxCalConfigBitD7D6D5D4D3 D2 D1 D0NamehardRecal VCOCAL[1:0] swResetTypeRRRRR/WR/WR/WR/WBit Name

Si504052 Rev. 1.3Reset settings = 0000 0000Register 9. RxAlarmStatusBitD7D6D5D4D3D2D1D0NamerefLOS LOS LOL fifoErr tpErrAlarm tpSyncLos sqmAlarmTypeRRR

Si5040Rev. 1.3 53Reset settings = 0000 0001Register 10. RxLosCtrlBitD7D6D5D4D3D2D1D0Name sqmLosEn dLosEn[1:0] aLosEnType RRRRR/W R/W R/WBit Name Funct

Si504054 Rev. 1.3Reset settings = 0000 0000Reset settings = 0000 1111Register 11. RxLosStatusBitD7D6D5 D4 D3 D2D1D0NamesqmLOS dLOSlastTrigger dLOS aLO

Si5040Rev. 1.3 55Reset settings = 0111 0000Reset settings = 0000 0000Register 13. aLosThresh2BitD7D6D5D4D3D2D1D0Name aLosHyst[3:0] Reserved aLosThresh

Si504056 Rev. 1.3Reset settings = 0000 0000Reset settings = 0000 0101Register 16. peakDetBitD7D6D5D4D3D2D1D0Name peakDet[1:0]Type RRBit Name Function7

Si5040Rev. 1.3 57Reset settings = 0110 0000Reset settings = 0001 0001Register 18. RxdLosClearThreshBitD7D6D5D4D3D2D1D0Name RxdLosClearThresh[7:0]Type

Si504058 Rev. 1.3Reset settings = 0000 0000Reset settings = 0000 0000Register 21. sliceLvlBitD7D6D5D4D3D2D1D0Name sliceLvl[7:0]Type R/WBit Name Functi

Si5040Rev. 1.3 59Reset settings = 0000 0000Reset settings = undefinedRegister 24. RxphaseAdjustBitD7D6D5D4D3D2D1D0Name RxphaseAdjust[6:0]Type RR/WBit

Si50406 Rev. 1.3Table 2. DC Characteristics (VDD= 1.8 V +5%/–10%, TA= –40 to 95 °C)Parameter Symbol Test Condition Min Typ Max UnitSupply Current IDD—

Si504060 Rev. 1.3Reset settings = 0010 1001Reset settings = 0000 1111Register 26. RxSqmConfigBitD7D6D5D4D3D2D1D0Name RxSqmThresh[5:0]Type R/W R/W R/WB

Si5040Rev. 1.3 61Reset settings = 0000 0010Register 28. RxdPathConfigBitD7D6D5D4D3D2 D1 D0Name dinvert clkOnLOS SquelchO-nRxLOLSquelchO-nRxLOSSquelch

Si504062 Rev. 1.3Reset settings = 0000 0000Register 29. RxtpSelBit D7 D6D5D4 D3 D2 D1 D0Name tpChkInvert tpChkSel[2:0] tpGenInvert tpGenSel[2:0]Type R

Si5040Rev. 1.3 63Reset settings = 0000 0010Reset settings = 1010 1010Register 30. RxtpChkConfigBit D7D6D5D4D3 D2 D1 D0NametpSyncMask tpTimeBase[1:0]Ty

Si504064 Rev. 1.3Reset settings = 1010 1010Reset settings = 1010 1010Reset settings = 1010 1010Register 32. RxtpArbGenPtnBit D15 D14 D13 D12 D11 D10 D

Si5040Rev. 1.3 65Reset settings = 1010 1010Reset settings = 1010 1010Reset settings = 1010 1010Register 35. RxtpArbGenPtnBit D39 D38 D37 D36 D35 D34 D

Si504066 Rev. 1.3Reset settings = 1010 1010Reset settings = 1010 1010Reset settings = 1010 1010Register 38. RxtpArbGenPtnBit D63 D62 D61 D60 D59 D58 D

Si5040Rev. 1.3 67Reset settings = 1010 1010Reset settings = 1010 1010Reset settings = 1010 1010Register 41. RxtpArbChkPtnBit D23 D22 D21 D20 D19 D18 D

Si504068 Rev. 1.3Reset settings = 1010 1010Reset settings = 1010 1010Reset settings = 1010 1010Register 44. RxtpArbChkPtnBit D47 D46 D45 D44 D43 D42 D

Si5040Rev. 1.3 69Reset settings = 1111 1111Reset settings = undefinedRegister 47. RxtpTargetErrBitD7D6D5D4D3D2D1D0Name RxtpTargetErr[7:0]Type R/WBit N

Si5040Rev. 1.3 7I2C Bus Lines (SD, SCK)Input Voltage Low VILI2C—— 0.3 x VDDIOVInput Voltage High VIHI2C0.7 x VDDIO——VInput Current III2CVIN= 0.1 x VDD

Si504070 Rev. 1.3Reset settings = undefinedReset settings = undefinedReset settings = undefinedRegister 49. RxtpChkErrCnt (40-bit Register)Bit D15 D14

Si5040Rev. 1.3 71Reset settings = undefinedReset settings = undefinedRegister 52. RxtpChkErrCnt (MSB of a 40-bit Register)Bit D39 D38 D37 D36 D35 D34

Si504072 Rev. 1.3Reset settings = 1111 0101Reset Settings = 1000 1101Register 56. OutputLevelBitD7D6D5D4D3 D2 D1 D0Name ReservedReservedoutLevel[2:0]T

Si5040Rev. 1.3 73Reset settings = 1010 0001Reset settings = 1110 0000Register 84. RxEqConfig1BitD7D6D5D4D3D2D1D0Name RxEqGain ReservedType R/W R/WBit

Si504074 Rev. 1.3Reset settings = 0001 1110Reset settings = 0000 0000Register 98. RxLoopFAcqBit D7 D6 D5 D4 D3 D2 D1 D0Name RxLoopFAcqCtl RxLoopFAcq[6

Si5040Rev. 1.3 75Reset settings = 0000 0000Reset settings = 0000 0000Register 107. sqmLOLThreshBit D7 D6 D5 D4 D3 D2 D1 D0Name sqmLOLThresh[0] Reserve

Si504076 Rev. 1.3Reset settings = 0000 0000Reset settings = 0010 0010Register 109. sqmLOLThreshBitD7D6D5D4D3D2D1D0Name Reserved sqmLOLThresh[13:9]Type

Si5040Rev. 1.3 77Reset settings = 0000 0000Register 132. TxintMaskBitD7D6D5D4D3D2D1D0Name refLOS LOS LOL fifoErr tpErrAlarm tpSyncLos sqmAlarmType R R

Si504078 Rev. 1.3Reset settings = 0000 0000Register 133. TxintStatus (Sticky Bits)BitD7D6D5D4D3D2D1D0Name refLOS LOS LOL fifoErr tpErrAlarm tpSyncLos

Si5040Rev. 1.3 79Reset settings = 0100 0000Register 134. TxCmuConfigBitD7D6D5D4D3D2D1D0Name cmuBandwidth[3:0] cmuMode[2:0]Type R/W R R/WBit Name Funct

Si50408 Rev. 1.3Table 3. AC Characteristics–RXDIN (Receiver Input)(VDD= 1.8 V +5/–10%, TA= –40 to 95 C)Parameter Symbol Test Condition Min Typ Max Un

Si504080 Rev. 1.3Reset settings = 1001 0100Register 135. TxConfigBit D7 D6 D5 D4 D3 D2 D1 D0Name CDRLTDATA uselolMode lolMode ltrType R/W RBit Name Fu

Si5040Rev. 1.3 81Reset settings = 0000 0000Register 136. TxCalConfigBitD7D6D5D4D3 D2 D1 D0Name hardRecal VCOCAL[1:0] swResetType RRRRR/WR/WR/WR/WBit N

Si504082 Rev. 1.3Reset settings = 0000 0000Register 137. TxAlarmStatusBitD7D6D5D4D3D2D1D0Name refLOS LOS LOL fifoErr tpErrAlarm tpSyncLos sqmAlarmType

Si5040Rev. 1.3 83Reset settings = 0000 1110Reset settings = 0000 0000Register 138. TxLosCtrlBitD7D6D5D4D3D2D1D0Name sqmLosEn dLosEn[1:0]Type RR/WR/WRB

Si504084 Rev. 1.3Reset settings = 0000 0000Reset settings = 0110 0000Register 145. TxdLosAssertThreshBitD7D6D5D4D3D2D1D0Name TxdLosAssertThresh[7:0]Ty

Si5040Rev. 1.3 85Reset settings = 0000 0000Reset settings = 0000 0000Register 152. TxphaseAdjustBitD7D6D5D4D3D2D1D0Name TxphaseAdjust[6:0]Type RR/WBit

Si504086 Rev. 1.3Reset settings = 0000 0101Reset settings = 0000 1000Register 154. TxSqmConfigBitD7D6D5D4D3D2D1D0Name TxSqmThresh[5:0]Type R/W R/W R/W

Si5040Rev. 1.3 87Reset settings = 0000 0010Register 156. TxdPathConfigBit D7 D6 D5 D4 D3 D2 D1 D0Name dinvert clkOnLOS SquelchOnTxLOL SquelchOnTxLOS S

Si504088 Rev. 1.3Reset settings = 0000 0000Register 157. TxtpSelBit D7 D6 D5 D4 D3 D2D1D0Name tpChkInvert tpChkSel[2:0] tpGenInvert tpGenSel[2:0]Type

Si5040Rev. 1.3 89Reset settings = 0000 0010Reset settings = 1010 1010Register 158. TxtpChkConfigBitD7D6D5D4D3 D2 D1 D0Name tpSyncMask tpTimeBase[1:0]T

Si5040Rev. 1.3 9Table 4. AC Characteristics—RD (Receiver Output)(VDD= 1.8 V +5/–10%, TA= –40 to 95 C)Parameter Symbol Test Condition Min Typ Max Unit

Si504090 Rev. 1.3Reset settings = 1010 1010Reset settings = 1010 1010Reset settings = 1010 1010Register 160. TxtpArbGenPtnBit D15 D14 D13 D12 D11 D10

Si5040Rev. 1.3 91Reset settings = 1010 1010Reset settings = 1010 1010Reset settings = 1010 1010Register 163. TxtpArbGenPtnBit D39 D38 D37 D36 D35 D34

Si504092 Rev. 1.3Reset settings = 1010 1010Reset settings = 1010 1010Reset settings = 1010 1010Register 166. TxtpArbGenPtnBit D63 D62 D61 D60 D59 D58

Si5040Rev. 1.3 93Reset settings = 1010 1010Reset settings = 1010 1010Reset settings = 1010 1010Register 169. TxtpArbChkPtnBit D23 D22 D21 D20 D19 D18

Si504094 Rev. 1.3Reset settings = 1010 1010Reset settings = 1010 1010Reset settings = 1010 1010Register 172. TxtpArbChkPtnBit D47 D46 D45 D44 D43 D42

Si5040Rev. 1.3 95Reset settings = 1111 1111Reset settings = undefinedRegister 175. TxtpTargetErrBitD7D6D5D4D3 D2 D1 D0Name TxtpTargetErr[7:0]Type R/WB

Si504096 Rev. 1.3Reset settings = undefinedReset settings = undefinedReset settings = undefinedRegister 177. TxtpChkErrCnt (40-bit Register)Bit D15 D1

Si5040Rev. 1.3 97Reset settings = undefinedReset settings = undefinedRegister 180. TxtpChkErrCnt (MSB of a 40-bit Register)Bit D39 D38 D37 D36 D35 D34

Si504098 Rev. 1.3Reset settings = 1111 0101Register 184. OutputLevelBitD7D6D5D4D3 D2 D1 D0Name HsPowerCtl[1:0]ReservedoutLevel[2:0]Type R/WR/WR/WBit N

Si5040Rev. 1.3 99Reset settings = 1000 1101Reset settings = 0001 1110Register 205. TxPDGainAcqBitD7D6D5D4D3 D2 D1 D0Name TxPDGainAcq[2:0]ReservedType